Phase locked loop circuits are well known in the data processing art as clock generators which provide stable clock signals having predetermined, stable frequencies. The stability of each frequency is provided as a result of an iterative process which uses a feedback path to compare an output of the phase lock loop circuit with an input signal typically provided by a crystal oscillator.
During execution of this iterative process, a lock detect circuit generally indicates that a lock condition has been satisfied when the feedback provided by the phase lock loop circuit is at a level which is within a certain percentage of a crystal oscillator frequency. When lock is first detected, the feedback frequency may surpass, or overshoot, the crystal oscillator frequency. The feedback frequency is then decreased until it is lower than the crystal oscillator frequency. In such a case, the feedback frequency continues to oscillate around the crystal oscillator frequency of the crystal oscillator until it is within the certain percentage of the frequency of the crystal oscillator. At that point in time, the phase lock loop is said to have achieved lock. However, during the period of time in which the feedback frequency is overshooting and undershooting the frequency of the crystal oscillator, the lock detect circuit may erroneously indicate that lock is achieved.
Many variations of the phase lock loop circuit have been developed to provide improvements over this technology. For example, U.S. Pat. No. 4,929,916, describes a phase lock detection circuit which does not generate an erroneous lock signal during the transient process of the output of the phase lock loop circuit towards the crystal oscillator. The phase lock detection circuit disclosed in U.S. Pat. No. 4,929,916 generates a phase lock signal only when the output of the phase lock loop circuit satisfies the lock condition for a predetermined period of time. If the lock condition has been satisfied for the predetermined period of time, it may be concluded that a stable locked condition has been realized.
While the invention described in U.S. Pat. No. 4,929,916 provides a unique solution to determining a stable lock condition, the implementation of the invention requires the use of analog signals to perform a phase lock operation. Such use of analog signals is well known in the data processing art. However, because analog signals are used during phase match detection, small amounts of noise inherent in the circuitry used to implement the phase lock loop circuit may result in the lock condition of the circuit being either erroneously set or cleared. Such susceptibility to noise may result in the phase lock loop circuit providing incorrect and unreliable results. Additionally, because analog circuitry is typically required in phase lock loop circuitry, the accuracy of the analog circuitry is often sensitive to minimal variations in the processing parameters used to manufacture the phase lock loop circuit.
Phase lock loop circuits are generally susceptible to metastability which results in phase lock loop circuits that are not stable and may produce erroneous results. Additionally, the sensitivity to processing parameter variations exhibited by typical phase lock loop circuits may result in unreliable results and an inability of a designer to accurately predict an output of the phase lock loop circuit.